1. Field of the Invention
The present invention relates generally to electronic packaging technology and, more particularly, to semiconductor packages having improved chip-attaching structures and methods for manufacturing the semiconductor packages with improved chip-attaching reliability.
2. Description of the Related Art
In general, an electronic package or a semiconductor package is defined as the housing and interconnection of integrated circuits (also referred to as ‘semiconductor chips’, ‘chips’, or ‘die’) to form an electronic system. The functions which the package must provide include a structure to physically support the chip, a physical housing to protect the chip from the environment, an adequate means of removing heat generated by the chips or system, and electrical connections to allow signal and power access to and from the chip.
An example of a conventional semiconductor package is shown in FIG. 1. Referring to FIG. 1, the package 10 includes a semiconductor chip 11, a substrate 12, bonding wires 13, an adhesive layer 14, an encapsulating layer 15, and solder balls 17.
The chip 11 is disposed on an upper surface of the substrate 12, and the solder balls 17 are arranged on a lower surface of the substrate 12. The bonding wires 13 electrically connect chip pads 11a of the chip 11 and substrate pads 12a of the substrate 12. The adhesive layer 14 physically attaches and supports the chip 11 to the substrate 12. The encapsulating layer 15 protects the chip 11, the wires 13, and the upper surface of the substrate 12 from the environment.
The above-described conventional package 10 has drawbacks as follows.
First, adhesive material used for the adhesive layer 14 may often overflow beyond the boundary 11b of the chip 11. Unfortunately, an overflowing part 14a of the adhesive layer 14 tends to affect and contaminate the substrate pads 12a. This may result in poor bonding of the wires 13 on the substrate pads 12a. 
Second, the chip 11 and the substrate 12 may warp due to a difference in the coefficient of thermal expansion (CTE) during a chip attaching process and may be restored after the chip attaching process. This often causes what is called an under-coverage problem where the aforementioned overflowing part 14a enters between the chip 11 and the substrate 12.
Third, when the encapsulating layer 15 is formed, unfavorable adhesive voids may form between the chip 11 and the substrate 12. In most cases, such adhesive voids are a prime cause of low attaching reliability.